cc1100_cc2500.h

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/******************************************************************************
* Copyright (c) 2017, Alan Barr
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* * Redistributions of source code must retain the above copyright notice, this
*   list of conditions and the following disclaimer.
*
* * Redistributions in binary form must reproduce the above copyright notice,
*   this list of conditions and the following disclaimer in the documentation
*   and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************/

#ifndef __CCX_REGISTERS_H__
#define __CCX_REGISTERS_H__


/******************************************************************************/
/******************************************************************************/

#define CCX_REG_IOCFG2      0x00 
#define CCX_REG_IOCFG1      0x01 
#define CCX_REG_IOCFG0      0x02 
#define CCX_REG_FIFOTHR     0x03 
#define CCX_REG_SYNC1       0x04 
#define CCX_REG_SYNC0       0x05 
#define CCX_REG_PKTLEN      0x06 
#define CCX_REG_PKTCTRL1    0x07 
#define CCX_REG_PKTCTRL0    0x08 
#define CCX_REG_ADDR        0x09 
#define CCX_REG_CHANNR      0x0A 
#define CCX_REG_FSCTRL1     0x0B 
#define CCX_REG_FSCTRL0     0x0C 
#define CCX_REG_FREQ2       0x0D 
#define CCX_REG_FREQ1       0x0E 
#define CCX_REG_FREQ0       0x0F 
#define CCX_REG_MDMCFG4     0x10 
#define CCX_REG_MDMCFG3     0x11 
#define CCX_REG_MDMCFG2     0x12 
#define CCX_REG_MDMCFG1     0x13 
#define CCX_REG_MDMCFG0     0x14 
#define CCX_REG_DEVIATN     0x15 
#define CCX_REG_MCSM2       0x16 
#define CCX_REG_MCSM1       0x17 
#define CCX_REG_MCSM0       0x18 
#define CCX_REG_FOCCFG      0x19 
#define CCX_REG_BSCFG       0x1A 
#define CCX_REG_AGCCTRL2    0x1B 
#define CCX_REG_AGCCTRL1    0x1C 
#define CCX_REG_AGCCTRL0    0x1D 
#define CCX_REG_WOREVT1     0x1E 
#define CCX_REG_WOREVT0     0x1F 
#define CCX_REG_WORCTRL     0x20 
#define CCX_REG_FREND1      0x21 
#define CCX_REG_FREND0      0x22 
#define CCX_REG_FSCAL3      0x23 
#define CCX_REG_FSCAL2      0x24 
#define CCX_REG_FSCAL1      0x25 
#define CCX_REG_FSCAL0      0x26 
#define CCX_REG_RCCTRL1     0x27 
#define CCX_REG_RCCTRL0     0x28 
#define CCX_REG_FSTEST      0x29 
#define CCX_REG_PTEST       0x2A 
#define CCX_REG_AGCTEST     0x2B 
#define CCX_REG_TEST2       0x2C 
#define CCX_REG_TEST1       0x2D 
#define CCX_REG_TEST0       0x2E 
/******************************************************************************/

/******************************************************************************/

#define CCX_REG_STROBE_SRES      0x30 
#define CCX_REG_STROBE_SFSTXON   0x31 
#define CCX_REG_STROBE_SXOFF     0x32 
#define CCX_REG_STROBE_SCAL      0x33 
#define CCX_REG_STROBE_SRX       0x34 
#define CCX_REG_STROBE_STX       0x35 
#define CCX_REG_STROBE_SIDLE     0x36 
#define CCX_REG_STROBE_SWOR      0x38 
#define CCX_REG_STROBE_SPWD      0x39 
#define CCX_REG_STROBE_SFRX      0x3A 
#define CCX_REG_STROBE_SFTX      0x3B 
#define CCX_REG_STROBE_SWORRST   0x3C 
#define CCX_REG_STROBE_SNOP      0x3D 
/******************************************************************************/

/******************************************************************************/
#define CCX_REG_STATUS_PARTNUM      0x30 
#define CCX_REG_STATUS_VERSION      0x31 
#define CCX_REG_STATUS_FREQEST      0x32 
#define CCX_REG_STATUS_LQI          0x33 
#define CCX_REG_STATUS_RSSI         0x34 
#define CCX_REG_STATUS_MARCSTATE    0x35 
#define CCX_REG_STATUS_WORTIME1     0x36 
#define CCX_REG_STATUS_WORTIME0     0x37 
#define CCX_REG_STATUS_PKTSTATUS    0x38 
#define CCX_REG_STATUS_VCO_VC_DAC   0x39 
#define CCX_REG_STATUS_TXBYTES      0x3A 
#define CCX_REG_STATUS_RXBYTES      0x3B 
/******************************************************************************/
/* Status Register: MARCSTATE */
/******************************************************************************/

typedef enum {
    CCX_MARCSTATE_SLEEP              = 0x00, 
    CCX_MARCSTATE_IDLE               = 0x01, 
    CCX_MARCSTATE_XOFF               = 0x02, 
    CCX_MARCSTATE_VCOON_MC           = 0x03, 
    CCX_MARCSTATE_REGON_MC           = 0x04, 
    CCX_MARCSTATE_MANCAL             = 0x05, 
    CCX_MARCSTATE_VCOON              = 0x06, 
    CCX_MARCSTATE_REGON              = 0x07, 
    CCX_MARCSTATE_STARTCAL           = 0x08, 
    CCX_MARCSTATE_BWBOOST            = 0x09, 
    CCX_MARCSTATE_FS_LOCK            = 0x0A, 
    CCX_MARCSTATE_IFADCON            = 0x0B, 
    CCX_MARCSTATE_ENDCAL             = 0x0C, 
    CCX_MARCSTATE_RX                 = 0x0D, 
    CCX_MARCSTATE_RX_END             = 0x0E, 
    CCX_MARCSTATE_RX_RST             = 0x0F, 
    CCX_MARCSTATE_TXRX_SWITCH        = 0x10, 
    CCX_MARCSTATE_RXFIFO_OVERFLOW    = 0x11, 
    CCX_MARCSTATE_FSTXON             = 0x12, 
    CCX_MARCSTATE_TX                 = 0x13, 
    CCX_MARCSTATE_TX_END             = 0x14, 
    CCX_MARCSTATE_RXTX_SWITCH        = 0x15, 
    CCX_MARCSTATE_TXFIFO_UNDERFLOW   = 0x16  
} CcxMarcState;

#define CCX_MARCSTATE_GET_STATE(_MS)     CCX_GET_BITS_VALUE((_MS), 5, 0)


#define CCX_MARCSTATE_IS_IN_TX(_MS)                            \
    (CCX_MARCSTATE_GET_STATE((_MS)) == CCX_MARCSTATE_FSTXON || \
    CCX_MARCSTATE_GET_STATE((_MS)) == CCX_MARCSTATE_TX      || \
    CCX_MARCSTATE_GET_STATE((_MS)) == CCX_MARCSTATE_TX_END)

/******************************************************************************/
/* Status Register: PKTSTATUS */
/******************************************************************************/
#define CCX_PKTSTATUS_GET_CRC_OK(_PS)      CCX_GET_BITS_VALUE((_PS), 1, 7)

/* @brief Obtain CS from contents of the Packet Status register.
 * @param _PS Value obtained from reading @ref CCX_REG_STATUS_PKTSTATUS.
 * @return Single bit Carrier Sense (CS) value.
 */
#define CCX_PKTSTATUS_GET_PQT_REACHED(_PS) CCX_GET_BITS_VALUE((_PS), 1, 5) 

#define CCX_PKTSTATUS_GET_PQT_REACHED(_PS) CCX_GET_BITS_VALUE((_PS), 1, 5) 

#define CCX_PKTSTATUS_GET_CCA(_PS)         CCX_GET_BITS_VALUE((_PS), 1, 4)

#define CCX_PKTSTATUS_GET_SFD(_PS)         CCX_GET_BITS_VALUE((_PS), 1, 3)

#define CCX_PKTSTATUS_GET_GDO2(_PS)        CCX_GET_BITS_VALUE((_PS), 1, 2)

#define CCX_PKTSTATUS_GET_GDO0(_PS)        CCX_GET_BITS_VALUE((_PS), 1, 0)

/******************************************************************************/
/* Status Register: TXBYTES */
/******************************************************************************/
#define CCX_TX_FIFO_MAX                  64

#define CCX_TX_BYTES_IS_UNDERFLOW(_TX)   CCX_GET_BITS_VALUE(_TX, 1, 7)

#define CCX_TX_BYTES_IN_FIFO(_TX)        CCX_GET_BITS_VALUE(_TX, 7, 0)

/******************************************************************************/
/* Status Register: RXBYTES */
/******************************************************************************/
#define CCX_RX_FIFO_MAX                  64

#define CCX_RX_BYTES_IS_OVERFLOW(_RX)    CCX_GET_BITS_VALUE(_RX, 1, 7)

#define CCX_RX_BYTES_IN_FIFO(_RX)        CCX_GET_BITS_VALUE(_RX, 7, 0)




/******************************************************************************/
/******************************************************************************/
#define CCX_REG_MULTIBYTE_PATABLE   0x3E 
#define CCX_REG_MULTIBYTE_TXFIFO    0x3F 
#define CCX_REG_MULTIBYTE_RXFIFO    0x3F 
/******************************************************************************/

/******************************************************************************/


#define CCX_MASK(_WIDTH, _OFFSET)                        \
            (((2<<(_WIDTH - 1)) - 1) << (_OFFSET))

#define CCX_GET_BITS_VALUE(_BITFIELD, _WIDTH, _OFFSET)   \
            (((_BITFIELD) & (CCX_MASK(_WIDTH, _OFFSET))) >> _OFFSET)


/******************************************************************************/
/* Header Byte */
/******************************************************************************/

#define CCX_HEADER_READ      CCX_MASK(1,7)

#define CCX_HEADER_BURST     CCX_MASK(1,6)

#define CCX_HEADER_ADDRESS   CCX_MASK(6,0)

/******************************************************************************/
/* Chip Status Byte */
/******************************************************************************/

typedef enum {
    CCX_STATE_IDLE               = 0X0, 
    CCX_STATE_RX                 = 0X1, 
    CCX_STATE_TX                 = 0X2, 
    CCX_STATE_FSTXON             = 0X3, 
    CCX_STATE_CALIBRATE          = 0X4, 
    CCX_STATE_SETTLING           = 0X5, 
    CCX_STATE_RXFIFO_OVERFLOW    = 0X6, 
    CCX_STATE_TXFIFO_UNDERFLOW   = 0X7  
} Cc1101ChipStatusState;

/* CC1101 Chip Status Byte Bit Masks */

#define CCX_SB_GET_STATE(_SB)                CCX_GET_BITS_VALUE(_SB, 3, 4)

#define CCX_SB_GET_FIFO_BYTES_AVAILABLE(_SB) CCX_GET_BITS_VALUE(_SB, 4, 0)

/******************************************************************************/
/* CC1101 Appended Bytes */
/******************************************************************************/

#define CCX_APD_B0_GET_RSSI(_BYTE0)  (_BYTE0)                  

#define CCX_APD_B1_IS_CRC_OK(_BYTE1) ((_BYTE1) & CCX_MASK(1,7))

#define CCX_APD_B1_GET_LQI(_BYTE1)   (CCX_GET_BITS_VALUE((_BYTE1),7,0))


#endif